{"q":"risc-v","hits":[{"collection":"cards","id":"suse","snippet":"ned a 25 June 2026 MoU with OpenChip to certify a sovereign RISC-V stack silicon-to-software. It even shipped a SEAL self-assessment tool.\",\"maturity\":\"Producti"},{"collection":"cards","id":"openchip","snippet":"\":\"openchip\",\"layer\":\"design\",\"tier\":\"eu\",\"name\":\"OpenChip (RISC-V, DARE)\",\"score\":4,\"tag\":\"Barcelona's open-ISA bet for HPC-AI.\",\"what\":\"Leads the RISC-V vecto"},{"collection":"cards","id":"dare-chiplets","snippet":"odasip (DARE chiplets)\",\"score\":3,\"tag\":\"The other two DARE RISC-V chiplets.\",\"what\":\"Axelera AI leads the AI-inference chiplet (Titania; EUR 61.6M DARE grant) "},{"collection":"cards","id":"riscv-others","snippet":"Quintauris, Semidynamics, VSORA\",\"score\":3,\"tag\":\"The wider RISC-V and accelerator field.\",\"what\":\"Quintauris (Bosch/Infineon/Nordic/NXP/Qualcomm automotive RIS"},{"collection":"cards","id":"arm","snippet":", now competing with the licensees it used to only sell to. RISC-V (OpenChip, Codasip, Quintauris) is the sovereignty hedge against exactly this ISA-licensing d"},{"collection":"cards","id":"x86","snippet":"tes and clouds. A real dependency, but not a break: Arm and RISC-V server alternatives exist and ship.\",\"maturity\":\"Incumbent\",\"weak\":\"Ubiquity: the installed b"},{"collection":"layers","id":"design","snippet":":\"Several credible European design bets and ISA control via RISC-V: Europe can draw its own chips. The accelerator incumbent still owns the market they are draw"},{"collection":"partners","id":"openchip->suse#0","snippet":"{\"a\":\"openchip\",\"b\":\"suse\",\"label\":\"MoU: sovereign RISC-V + SUSE stack\",\"year\":2026,\"src\":\"SUSE\",\"url\":\"https://www.suse.com/news/suse-and-openchip-par"},{"collection":"partners","id":"openchip->dare-chiplets#6","snippet":"{\"a\":\"openchip\",\"b\":\"dare-chiplets\",\"label\":\"DARE RISC-V chiplets\",\"year\":2025,\"src\":\"EuroHPC\",\"url\":\"https://www.eurohpc-ju.europa.eu/research-innova"},{"collection":"cases","id":"dare-sga1","snippet":"{\"id\":\"dare-sga1\",\"name\":\"DARE SGA 1 (RISC-V chiplets for European supercomputers)\",\"country\":\"EU\",\"year\":2025,\"status\":\"disbursed\",\"headl"},{"collection":"consortia","id":"101202459","snippet":"02459\",\"acronym\":\"DARE SGA 1\",\"title\":\"Digital Autonomy for RISC-V in Europe (Specific Grant Agreement 1)\",\"start\":\"2025-03-01\",\"status\":\"SIGNED\",\"url\":\"https:/"},{"collection":"consortia","id":"101194371","snippet":"{\"id\":\"101194371\",\"acronym\":\"Rigoletto\",\"title\":\"RISC-V GENERATION OF  HIGH PERFORMANCE AUTOMOTIVE PROCESSORS AND COMPUTING PLATFORMS\",\"start\":\"2025-"},{"collection":"consortia","id":"101092993","snippet":"{\"id\":\"101092993\",\"acronym\":\"RISER\",\"title\":\"RISC-V for Cloud Services\",\"start\":\"2023-01-01\",\"status\":\"SIGNED\",\"url\":\"https://cordis.europa.eu/pr"},{"collection":"consortia","id":"101095947","snippet":"{\"id\":\"101095947\",\"acronym\":\"TRISTAN\",\"title\":\"Together for RISc-V Technology and ApplicatioNs\",\"start\":\"2022-12-01\",\"status\":\"SIGNED\",\"url\":\"https://cordis.eur"},{"collection":"orgs","id":"dare-chiplets","snippet":"02459\",\"acronym\":\"DARE SGA 1\",\"title\":\"Digital Autonomy for RISC-V in Europe (Specific Grant Agreement 1)\",\"start\":\"2025-03-01\",\"end\":\"2028-02-29\",\"signed\":\"202"},{"collection":"orgs","id":"openchip","snippet":"{\"card\":\"openchip\",\"name\":\"OpenChip (RISC-V, DARE)\",\"entities\":[\"OPENCHIP SOFTWARE TECHNOLOGIES SL\"],\"projects\":4,\"contracted_eu\":1366608"},{"collection":"orgs","id":"riscv-others","snippet":"id/101145339\"},{\"id\":\"101092993\",\"acronym\":\"RISER\",\"title\":\"RISC-V for Cloud Services\",\"start\":\"2023-01-01\",\"end\":\"2026-12-31\",\"signed\":\"2022-12-01\",\"status\":\"S"},{"collection":"orgs","id":"siemens-eda","snippet":"{\"id\":\"101095947\",\"acronym\":\"TRISTAN\",\"title\":\"Together for RISc-V Technology and ApplicatioNs\",\"start\":\"2022-12-01\",\"end\":\"2026-06-30\",\"signed\":\"2022-11-27\",\"s"}]}