{"collection":"cards","total":12,"returned":12,"rows":[{"id":"sipearl","layer":"design","tier":"eu","name":"SiPearl (Rhea1)","score":3,"tag":"Europe's HPC CPU. Powered on, in bring-up.","what":"French. Rhea1 taped out (TSMC N6, 80 Arm Neoverse V1 cores) and powered on 13 May 2026, now in a bring-up and functional-validation phase with availability targeted end-2026. Headed into JUPITER's CPU cluster. EUR 130M Series A; Series B not announced as closed. Named in the EUR 290M IT4LIA AI Factory contract (Bologna, 22 Apr 2026), whose inference partition pairs SiPearl CPUs with Axelera accelerators: the one published European system configuration that is not all-Nvidia.","maturity":"Bring-up 2026","weak":"Arm ISA (not EU) + TSMC manufacturing. European design, borrowed foundations.","axes":{"capability":"emerging","jurisdiction":"eu","op_control":"european","substitutability":"hard"},"axes_note":"Rhea1 powered on May 2026, sampling; Arm ISA and TSMC manufacturing are the borrowed foundations (import spine).","depends_on":["leading-edge-fabs","arm"],"roadmap":{"claim":"Rhea1 sampling, then JUPITER's CPU cluster","year":2026,"source":"heise","url":"https://www.heise.de/en/news/Europe-s-most-complex-server-processor-is-running-11308863.html"}},{"id":"openchip","layer":"design","tier":"eu","name":"OpenChip (RISC-V, DARE)","score":4,"tag":"Barcelona's open-ISA bet for HPC-AI.","what":"Leads the RISC-V vector-accelerator chiplet (VEC) in EuroHPC's DARE project (EUR 240M, BSC-coordinated, 38 partners). RISC-V gives architectural control Arm cannot.","maturity":"Build-out","weak":"Early: design wins, packaging, compilers and software maturity all still to prove. First silicon is published rather than inferred: Openchip announced BER10 on 30 July 2026, a Linux-capable 64-bit RISC-V processor on a sub-2nm Gate-All-Around process, stating tape-out in 2025 and silicon in hand. No volume-production date, named customer or independent benchmark has been published, and the data-centre accelerator the DARE work points at is still to come. Ownership: Spain's Council of Ministers approved a SETT investment of over EUR 115m on 29 June 2026.","axes":{"capability":"emerging","jurisdiction":"eu","op_control":"european","substitutability":"hard"},"axes_note":"DARE VEC-chiplet lead; RISC-V gives ISA control the Arm route cannot; first silicon published July 2026, the data-centre accelerator still to come.","roadmap":{"claim":"VEC vector chiplet tape-out within DARE SGA1's three-year run (TSMC 7nm or below)","year":2028,"source":"eeNews Europe","url":"https://www.eenewseurope.com/en/e240m-dare-project-for-ai-risc-v-chiplets/"}},{"id":"dare-chiplets","layer":"design","tier":"eu","name":"Axelera, Codasip (DARE chiplets)","score":3,"tag":"The other two DARE RISC-V chiplets.","what":"Axelera AI leads the AI-inference chiplet (Titania; EUR 61.6M DARE grant) from edge to server class; Codasip leads the general-purpose RISC-V processor. Inference at the edge is a plausible European beachhead. First procurement evidence landed on 22 Apr 2026: the EUR 290M IT4LIA AI Factory contract in Bologna carries a dedicated inference partition on Axelera accelerators alongside SiPearl CPUs. EuroHPC buying European silicon, not only funding it. The release names the company, not the DARE chiplet, so do not read it as a Titania order.","maturity":"Development","weak":"Datacentre-class parts are years from volume; software ecosystem nascent. Consortium risk: Codasip divested its low-end RISC-V processor business to an unnamed public US semiconductor company on 8 Apr 2026 and pivoted to CHERI. DARE states all project activities continue as planned and it is in dialogue with Codasip and EuroHPC JU; no replacement has been named.","axes":{"capability":"emerging","jurisdiction":"eu","op_control":"european","substitutability":"hard"},"axes_note":"Titania and the DARE general-purpose part are in development; edge inference is the plausible beachhead, datacentre class is years out.","roadmap":{"claim":"First Titania-powered systems","year":2027,"source":"Axelera AI","url":"https://community.axelera.ai/product-updates/the-future-of-ai-inference-introducing-titania-133"}},{"id":"riscv-others","layer":"design","tier":"eu","name":"Quintauris, Semidynamics, VSORA","score":3,"tag":"The wider RISC-V and accelerator field.","what":"Quintauris (Bosch/Infineon/Nordic/NXP/Qualcomm automotive RISC-V JV, STMicro sixth shareholder), Semidynamics (RISC-V cores, strategic investment from SK hynix Apr 2026, amount undisclosed), VSORA and GreenWaves (edge AI). VSORA's Jotunn8 datacentre inference accelerator taped out in 2025 and, in VSORA's own words on 18 Jun 2026, 'is entering manufacturing': no silicon back, no samples, no deployment. Scaleway has committed to be the first production deployment.","maturity":"Mixed; nothing at volume","weak":"Fragmentation; no design wins at volume yet. The Jotunn8 commitment is forward-looking: an agreement to deploy the first chips VSORA produces, with no date, no volume and no named end customer.","axes":{"capability":"emerging","jurisdiction":"eu","op_control":"european","substitutability":"hard"},"axes_note":"A real but fragmented contender field; few volume design wins yet.","roadmap":{"claim":"Jotunn8 volume production (taped out Oct 2025, TSMC 5nm)","year":2026,"source":"VSORA","url":"https://vsora.com/vsora-announces-tape-out-of-game-changing-inference-chip-putting-europe-at-the-forefront-of-data-center-ai/"}},{"id":"euclyd","layer":"design","tier":"eu","name":"Euclyd (CRAFTWERK)","score":2,"tag":"Europe's newest accelerator bet still leaves Europe to get made.","what":"Dutch (Eindhoven) AI-inference silicon startup, founded 2024 by ex-ASML director Bernardo Kastrup. CRAFTWERK is a European-designed inference SiP aimed squarely at the Nvidia gap; a multi-chiplet system is targeted for 2028, and the company is seeking a raise of at least EUR 100M (backers include ex-ASML CEO Peter Wennink).","maturity":"Prototype","weak":"Unproven at scale; efficiency claims not independently validated. Design is European, manufacturing is not: implemented by Korea's ADTechnology (a Samsung Foundry Design Solution Partner) on Samsung FinFET. Not in the EU DARE consortia.","axes":{"capability":"emerging","jurisdiction":"eu","op_control":"european","substitutability":"hard"},"axes_note":"Prototype-stage Dutch design; fabrication sits with ADTechnology on Samsung Foundry FinFET (Nov 2025): European design, imported manufacturing.","depends_on":["leading-edge-fabs"],"roadmap":{"claim":"Multi-chiplet CRAFTWERK system targeted","year":2028,"source":"CNBC","url":"https://www.cnbc.com/2026/04/17/nvidia-rivals-chip-market-funding-ai-asml-euclyd.html"}},{"id":"quantum","layer":"design","tier":"eu","name":"Quantum: IQM, Pasqal, Alice&Bob","score":4,"tag":"Where Europe is genuinely at the front.","what":"IQM (Finland) delivering Radiance systems into LRZ's Euro-Q-Exa (54-qubit done, 150-qubit by end-2026); Pasqal (France) delivered a 140-qubit neutral-atom system to CINECA; Alice&Bob in France's EUR 500M PROQCIMA fault-tolerance programme.","maturity":"Deploying","weak":"Pre-advantage; real workloads still limited. But the lead is real.","axes":{"capability":"credible","jurisdiction":"eu","op_control":"european","substitutability":"swappable"},"axes_note":"Delivered systems (LRZ, CINECA) and multiple European vendors: rare depth, still pre-advantage."},{"id":"photonics","layer":"design","tier":"eu","name":"Q.ANT (photonic) + analog","score":3,"tag":"A different computing substrate Europe can own.","what":"Q.ANT (Germany) builds photonic processors for energy-efficient compute, a lane where the incumbents have no lock-in. Part of Europe's 'win on the next substrate' bet.","maturity":"Early","weak":"Unproven at scale; niche software ecosystem.","axes":{"capability":"emerging","jurisdiction":"eu","op_control":"european","substitutability":"hard"},"axes_note":"Early-stage bet on a substrate without incumbents; effectively sole-source in Europe today."},{"id":"arm","layer":"design","tier":"dependency","name":"Arm (ISA licensing)","score":2,"tag":"Europe's CPUs are designed on an ISA licensed from outside the EU.","what":"The dominant CPU instruction-set architecture. Born in Cambridge, but SoftBank-owned and Nasdaq-listed since 2023 (SoftBank ~90%). Almost every European CPU effort licenses it: SiPearl's Rhea1 runs 80 Arm Neoverse V1 cores. March 2026: Arm shipped its first in-house chip in 35 years, now competing with the licensees it used to only sell to. RISC-V (OpenChip, Codasip, Quintauris) is the sovereignty hedge against exactly this ISA-licensing dependency.","maturity":"Incumbent","weak":"European heritage, non-European control: the ISA and its licensing terms sit with SoftBank and US markets, not the EU. Licensable and shippable (SiPearl proves it), so a dependency, not one of the map's two hard breaks.","axes":{"capability":"proven","jurisdiction":"extra_eu","op_control":"foreign","substitutability":"hard"},"axes_note":"SoftBank-owned ISA: licensable and shippable (SiPearl proves it): hard, not locked; RISC-V is the hedge."},{"id":"nvidia-cuda","layer":"design","tier":"dependency","name":"Nvidia + CUDA","score":1,"tag":"The AI accelerator, and the software moat under everything.","what":"Nvidia's GPUs are the de-facto AI compute substrate and CUDA is the software moat under nearly every stack, European models included. One of the map's two hard breaks: no European accelerator at production scale.","maturity":"Incumbent","weak":"Locked in by software as much as silicon: CUDA, not the GPU, is the hardest part to substitute.","axes":{"capability":"proven","jurisdiction":"extra_eu","op_control":"foreign","substitutability":"locked"},"axes_note":"One of the two hard breaks: the accelerator and its CUDA moat have no European substitute at datacentre scale.","depends_on":["leading-edge-fabs"]},{"id":"x86","layer":"design","tier":"dependency","name":"Intel / AMD x86","score":2,"tag":"The default server ISA: borrowed, but substitutable.","what":"Intel and AMD's x86 runs most European server estates and clouds. A real dependency, but not a break: Arm and RISC-V server alternatives exist and ship.","maturity":"Incumbent","weak":"Ubiquity: the installed base and software assumptions keep x86 sticky even where alternatives exist.","axes":{"capability":"proven","jurisdiction":"extra_eu","op_control":"foreign","substitutability":"hard"},"axes_note":"A dependency, not a break: Arm-based and RISC-V server silicon ship today, so substitution is hard, not locked."},{"id":"siemens-eda","layer":"design","tier":"eu","name":"Siemens EDA","score":4,"tag":"Europe owns a chip-design chokepoint.","what":"Electronic Design Automation is the software without which no chip is designed, and the world's number three EDA vendor is wholly owned by Siemens AG of Germany, acquired as Mentor Graphics in 2017. Its Calibre physical-verification tool is foundry-mandated for signoff. In May 2026 Siemens signed a strategic framework agreement with the European Chips Joint Undertaking to supply EDA software to smaller companies, startups and research institutions at pre-defined pricing through the EuroCDP project, the first software provider to do so.","maturity":"Production","weak":"Strong in verification, absent in implementation. Synthesis, place-and-route and timing signoff remain US-owned, so a European design still cannot reach tape-out on European tools alone.","axes":{"capability":"proven","jurisdiction":"eu","op_control":"european","substitutability":"locked"},"axes_note":"German-owned and EU-jurisdiction, but Calibre's foundry-mandated position is a concentration: Europe holds the chokepoint rather than a substitutable option."},{"id":"eda-dep","layer":"design","tier":"dependency","name":"Synopsys / Cadence (EDA)","score":1,"tag":"No European chip reaches tape-out without it.","what":"Synopsys and Cadence, both US-incorporated, dominate logic synthesis, place-and-route and timing signoff. Every European chip design (SiPearl, OpenChip, Axelera, Euclyd) runs through this toolchain, which sits under US export-control jurisdiction. The 2025 US export-licence episode covering EDA sales to China demonstrated the lever.","maturity":"Incumbent","weak":"A quieter dependency than the GPU and the fab, and arguably an earlier one: it binds at design time, before any silicon exists. No European alternative exists below Siemens EDA: Silvaco is US-listed, and open-source EDA in Europe is still funding calls rather than product.","axes":{"capability":"proven","jurisdiction":"extra_eu","op_control":"foreign","substitutability":"locked"},"axes_note":"Locked at design time, before any silicon exists: Siemens EDA covers verification but not synthesis, place-and-route or timing signoff, so no design reaches tape-out on European tools alone."}]}